  0 PAK 68/3, GAL U2:  Cache Control Logic, L2-Cache nach Reset aus bis 1.    DMA
  1 18-09-93   V2_RSTb    Holger Zimmermann @ PE
  2 %ID
  3       P2_RST
  4 %TYP
  5       GAL20V8A
  6 %PINS
  7  !ciout  mat2  a0  a1  !as_00  !bgack_20  !wr  !as_20       !dsack  !reset  siz1
  8  siz0  !dram  !twe2  !dwe3  !dwe1  !c2off  !dwe2  !tclr       !dwe0  !twe0  mat0
  9 %LOGIC
 10 
 11  dwe0.OE = VCC;
 12  dwe0  = dram * !tclr * as_20 *  as_00 *  wr *  mat0 * !a1 * !a0
 13        + dram * !tclr * as_20 *  as_00 * !wr * !mat0 * !a1 * dsack *              !ciout
 14        + dram * !tclr * as_20 *  as_00 * !wr *  dwe0 * !a1 * dsack *              !ciout;
 15 
 16  dwe1  = dram * !tclr * as_20 *  as_00 *  wr *  mat0 * !a1 * siz1
 17        + dram * !tclr * as_20 *  as_00 *  wr *  mat0 * !a1 * a0
 18        + dram * !tclr * as_20 *  as_00 *  wr *  mat0 * !a1 * !siz0
 19        + dram * !tclr * as_20 *  as_00 * !wr * !mat0 * !a1 * dsack *              !ciout
 20        + dram * !tclr * as_20 *  as_00 * !wr *  dwe1 * !a1 * dsack *              !ciout;
 21 
 22  dwe2  = dram * !tclr * as_20 *  as_00 *  wr *  mat2 *  a1 * !a0
 23        + dram * !tclr * as_20 *  as_00 * !wr * !mat2 *  a1 * dsack *              !ciout
 24        + dram * !tclr * as_20 *  as_00 * !wr *  dwe2 *  a1 * dsack *              !ciout;
 25 
 26  dwe3  = dram * !tclr * as_20 *  as_00 *  wr *  mat2 *  a1 * siz1
 27        + dram * !tclr * as_20 *  as_00 *  wr *  mat2 *  a1 * a0
 28        + dram * !tclr * as_20 *  as_00 *  wr *  mat2 *  a1 * !siz0
 29        + dram * !tclr * as_20 *  as_00 * !wr * !mat2 *  a1 * dsack *              !ciout
 30        + dram * !tclr * as_20 *  as_00 * !wr *  dwe3 *  a1 * dsack *              !ciout;
 32  twe0  = dram * !tclr * as_20 *  as_00 * !wr *  dwe0 * !a1 * dsack *              !ciout
 33        + dram * !tclr * as_20 *  as_00 * !wr *  dwe1 * !a1 * dsack *              !ciout;
 34 
 35  twe2  = dram * !tclr * as_20 *  as_00 * !wr *  dwe2 *  a1 * dsack *              !ciout
 36        + dram * !tclr * as_20 *  as_00 * !wr *  dwe3 *  a1 * dsack *              !ciout;
 37 
 38  tclr  =  as_20 * tclr
 39        + !as_20 * bgack_20
 40        + !as_20 * reset
 41        + !as_20 * c2off;
 42 
 43  c2off.OE = !bgack_20;
 44  c2off    = reset                 ´SLC off nach Reset
 45           + c2off * !bgack_20;    ´notwendig für TOS 2.06 Speichertest
 46 
 47 %END